Freescale Semiconductor /MKV58F24 /MPU /RGDAAC7

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RGDAAC7

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0M0UM0M0SM 0 (M0PE)M0PE 0M1UM0M1SM 0 (M1PE)M1PE 0M2UM0M2SM 0 (M2PE)M2PE 0 (0)M3UM0 (00)M3SM 0 (0)M3PE 0 (0)M4WE 0 (0)M4RE 0 (0)M5WE 0 (0)M5RE 0 (0)M6WE 0 (0)M6RE 0 (0)M7WE 0 (0)M7RE

M7WE=0, M5RE=0, M3SM=00, M6RE=0, M5WE=0, M6WE=0, M4RE=0, M3PE=0, M4WE=0, M3UM=0, M7RE=0

Description

Region Descriptor Alternate Access Control n

Fields

M0UM

Bus Master 0 User Mode Access Control

M0SM

Bus Master 0 Supervisor Mode Access Control

M0PE

Bus Master 0 Process Identifier Enable

M1UM

Bus Master 1 User Mode Access Control

M1SM

Bus Master 1 Supervisor Mode Access Control

M1PE

Bus Master 1 Process Identifier Enable

M2UM

Bus Master 2 User Mode Access Control

M2SM

Bus Master 2 Supervisor Mode Access Control

M2PE

Bus Master 2 Process Identifier Enable

M3UM

Bus Master 3 User Mode Access Control

0 (0): An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

1 (1): Allows the given access type to occur

M3SM

Bus Master 3 Supervisor Mode Access Control

0 (00): r/w/x; read, write and execute allowed

1 (01): r/x; read and execute allowed, but no write

2 (10): r/w; read and write allowed, but no execute

3 (11): Same as User mode defined in M3UM

M3PE

Bus Master 3 Process Identifier Enable

0 (0): Do not include the process identifier in the evaluation

1 (1): Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

M4WE

Bus Master 4 Write Enable

0 (0): Bus master 4 writes terminate with an access error and the write is not performed

1 (1): Bus master 4 writes allowed

M4RE

Bus Master 4 Read Enable

0 (0): Bus master 4 reads terminate with an access error and the read is not performed

1 (1): Bus master 4 reads allowed

M5WE

Bus Master 5 Write Enable

0 (0): Bus master 5 writes terminate with an access error and the write is not performed

1 (1): Bus master 5 writes allowed

M5RE

Bus Master 5 Read Enable

0 (0): Bus master 5 reads terminate with an access error and the read is not performed

1 (1): Bus master 5 reads allowed

M6WE

Bus Master 6 Write Enable

0 (0): Bus master 6 writes terminate with an access error and the write is not performed

1 (1): Bus master 6 writes allowed

M6RE

Bus Master 6 Read Enable

0 (0): Bus master 6 reads terminate with an access error and the read is not performed

1 (1): Bus master 6 reads allowed

M7WE

Bus Master 7 Write Enable

0 (0): Bus master 7 writes terminate with an access error and the write is not performed

1 (1): Bus master 7 writes allowed

M7RE

Bus Master 7 Read Enable

0 (0): Bus master 7 reads terminate with an access error and the read is not performed

1 (1): Bus master 7 reads allowed

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